FIG. 1 illustrates a diagram of a source driver used in a LCD (Liquid Crystal Display) device. The source driver 100 shown in FIG. 1 comprises a shift register 102, a latch buffer 104, a level shifter 106 and a digital-to-analog converter (DAC) 108. The latch buffer 104 stores and outputs digital data signals by the control of the shift register 102. The level shifter 106 shifts voltage levels of the digital data signals to predetermined voltage levels. The digital-to-analog converter (DAC) 108 generates a driving voltage Vd to drive the LCD according to the outputted signals from the level shifter 106.
FIG. 2 illustrates a diagram of a conventional level shifter. As shown in FIG. 2, the level shifter 106 comprises a first transistor 202, a second transistor 204, a third transistor 206, a fourth transistor 208, and a fifth transistor 210. The first transistor 202 and the second transistor 204 are N type transistors while the third transistor 206, the fourth transistor 208 and the fifth transistor 210 are P type transistors. The first transistor 202 has a first source/drain connected to a reference voltage source VSSA, a second source/drain connected to an inverted output node OUTB, and a gate connected to an input node IN1 for receiving the digital data signal. The second transistor 204 has a first source/drain connected to the reference voltage source VSSA, a second source/drain connected to an output node OUT, and a gate connected to an inverted input node IN2 for receiving a signal corresponding to the opposite logic state of the digital data signal.
The third transistor 206 has a first source/drain connected to the inverted output node OUTB, a gate connected to the output node OUT, and a second source/drain. The fourth transistor 208 has a first source/drain connected to the output node OUT, a gate connected to the inverted output node OUTB, and a second source/drain connected to the second source/drain of the third transistor 206. The fifth transistor 210 has a first source/drain connected to the second source/drains of the third transistor 206 and the fourth transistor 208, a second source/drain connected to a high voltage source VDDA, and a gate connected to a reference voltage source VSSA.
When the input voltage inputted to the level shifter 106 via the input node IN1 decreases, the turning on and off of the first transistor 202 and the second transistor 204 of the level shifter is slow resulting in the late response of the third transistor 206 and the fourth transistor 208. Therefore, a DC current path along the first transistor 202 and the third transistor 206 occurs and thus increases the power consumption.